1. Field of the Invention
The present invention relates to a semiconductor device having a super junction structure and method of manufacturing the same.
2. Description of the Related Art
Conventionally, a vertical metal-oxide-semiconductor (MOS) transistor can be highly integrated compared with a horizontal MOS transistor. Thus, the vertical MOS transistor can be suitably used for an electrical application, for example, for controlling electric power. However, in the vertical MOS transistor, a high breakdown voltage and a low on resistance have a trade-off relationship therebetween.
A semiconductor device that has a PN column layer functioning as a super junction (SJ) as a drift layer, that is, an SJ-MOS can improve a trade-off relationship between the high breakdown voltage and the low on resistance. For example, U.S. Pat. No. 6,621,132 (corresponding to JP-2002-76339A), JP-2004-200441A, and US 2005/0006717A (corresponding to JP-2005-19528A) respectively disclose an SJ-MOS.
An SJ-MOS 100 according to a first example of the related art and an SJ-MOS 200 according to a second example of the related art will now be described with reference to FIGS. 9A and 9B.
The SJ-MOS 100 and SJ-MOS 200 have similar structures. Each of the SJ-MOS 100 and the SJ-MOS 200 is an N-channel SJ-MOS and has an N+ type silicon substrate 1 functioning as a drain region. The SJ-MOS 100 has a PN column layer 10 on the silicon substrate 1, and the SJ-MOS 200 has a PN column layer 30 on the silicon substrate 1. Each of the PN column layers 10 and 30 is an epitaxial layer made of silicon and includes N type columns 2n and P type columns 2p. The N type columns 2n and the P type columns 2p have approximately rectangular parallelepiped shapes and are alternately arranged on the silicon substrate 1. On each of the PN column layers 10 and 30, a P type layer 3 functioning as a channel-forming layer is formed by an epitaxial layer made of silicon or ion implantation. At surface portions of the P type layer 3, N+ type regions 4 functioning as source regions are formed.
The SJ-MOS 100 has trench insulation gate electrodes (gate electrodes) 20 that penetrate through the P type layer 3. The SJ-MOS 200 has trench insulation gate electrodes (gate electrodes) 40 that penetrate through the P type layer 3. Each of the gate electrodes 20 and 40 has an approximately rectangular parallelepiped shape and has a sidewall insulation layer 5 and an embedded polysilicon 6. In a case where conductivity types of each component in the SJ-MOS 100 and the SJ-MOS 200 are reversed, a P channel SJ-MOS is provided.
In the SJ-MOS 100 and the SJ-MOS 200, the gate electrodes 20 and 40 are arranged on the PN column layers 10 and 30, respectively, in different manners. In the SJ-MOS 100 shown in FIG. 9A, the PN column layer 10, the gate electrodes 20, and the N+ type regions 4 are arranged approximately parallel in a planar direction of the silicon substrate 1. In the SJ-MOS 200 shown in FIG. 9B, the gate electrodes 20 and the source regions 4 are arranged orthogonally to the PN column layer 30 in the planar direction of the silicon substrate 1. Alternatively, the gate electrodes may be arranged obliquely with respect to the PN column layer in the planar direction of the silicon substrate 1.
When the SJ-MOS 100 is manufactured, an alignment process for forming the gate electrodes 20 in a width Wn of the N type columns 2n is required for reducing an on resistance. In a case where the gate electrodes and the PN column layer are arranged orthogonally in the planar direction of silicon substrate 1, as the SJ-MOS 200 shown in FIG. 9B, the alignment process can be omitted. Thus, a production cost can be reduced.
In the SJ-MOS, it is required to reduce the on resistance and improve a switching speed (i.e., reducing a switching loss). The reduction of the on resistance and the reduction of a switching loss have a trade-off relation therebetween. In order to reduce the on resistance, arrangement densities of the gate electrodes 20 and 40 and arrangement densities of the N type columns 2n and the P type columns 2p in the PN column layers 10 and 30 are required to be high. In contrast, in order to reduce the switching loss, the arrangement densities of the gate electrodes 20 and 40 are required to be low for reducing gate capacitance. The capacitance changes in accordance with areas of the sidewall insulation layers 5. In a case where the PN column layer and the gate electrodes are arranged orthogonally in the planar direction of the silicon substrate 1, as the SJ-MOS 200, the arrangement of the gate electrode and the PN column layer is less limited and a design flexibility is large compared with a case where the PN column layer and the gate electrodes are arranged in parallel, as the SJ-MOS 100.
In a manufacturing method of the PN column layer 30 of the SJ-MOS 200, a plurality of trenches are formed in the silicon substrate 1 that has an n type conductivity, and the p type columns 2p are formed by an epitaxial growth so as to fill the trenches, for example. However, when the p type columns 2p are formed, a void may be generated in the PN column layer 30 depending on a condition, and thereby the high breakdown voltage may not be obtained and the leak current in the PN column layer 30 may increase.